1. Field of the Invention
The present invention relates to fault tolerant nano-circuitry, and particularly to a generalized modular redundancy fault tolerance method for combinational circuits.
2. Description of the Related Art
Nano-scale devices are continuously shrinking, operating at lower voltages and higher frequencies. This makes them more susceptible to environmental perturbations and distinguished by their high dynamic fault rates. The soft error rate (SER) produced by these effects may exceed the failure in time (FIT) specifications in various application domains. In such applications, soft-error mitigation schemes should be employed for both memories and logic. Redundancy techniques are widely used to increase the reliability of combinational logic circuits. All fault tolerance approaches rely on some sort of redundancy. Otherwise, there will be no way to tell that a device has changed its state into an incorrect one. Many researches have investigated increasing the reliability of circuits using various redundancy schemes. Their main concern is to increase reliability while minimizing the inevitable overhead of area, power, or time.
Thus, a generalized modular redundancy fault tolerance method for combinational circuits solving the aforementioned problems is desired.